The demand for increased functionality in both consumer and industrial electronics, coupled with the trend of miniaturization, continues to place complexity and size constraints on the packaging of electronic components, specifically the number of pins available on an electronic component, e.g., an integrated circuit (IC), passive device, or semiconductor. A preferred solution has been the development of the column grid array, or CGA, which provides a type of surface-mount packaging used to conduct electrical signals from the electronic component to the printed wiring board (PWB) the electronic component is placed on. Instead of using traditional pins to connect the component to the PWB, columns of solder are affixed to the bottom of the component substrate and attached to the PWB, creating an array of columns.
A primary disadvantage of CGAs, however, is that the solder columns fatigue more rapidly than the traditional lead to pin connections do. Repeated periods of high thermal or mechanical stress followed by periods of relaxations in the interconnect area(s) eventually cause the solder joints to fracture. The fracture of a single solder joint, i.e., a single column, produces an open circuit or partial failure. Therefore, the CGA is not always a popular choice in certain fields, especially high reliability applications, which require an interconnection between the component and the PWB to be highly flexible during repeated intervals of thermal cycling. In particular, high reliability applications entail a more detailed material selection based on other properties, including exposure to extreme environments.
To overcome the effects of exposure to extreme environments in high reliability applications, the component is typically constructed of a ceramic substrate. However, use of the ceramic substrate material comes at an economic cost, particularly with an increased coefficient of thermal expansion (CTE) difference between the component and the PWB. The higher CTE value means that the interconnections between the component and PWB are subject to a higher amount of fatigue. The increased fatigue decreases the overall life of the packaged assembly. Therefore, current electronic assemblies using components with ceramic substrates are constrained to a limited capacity in an effort to reduce the effects of the difference in CTE values between the component and the PWB.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the specification, there is a need in the art for improved interconnections within a column grid array.